Fault Coverage Sample Clauses

Fault Coverage. Tab.1 reports the total number of deterministic test patterns (and test vectors) generated for each tested module, and the associated coverage. This latter was derived by means of an in-house made gate-level fault simulation framework: (one or more) faults are applied to any or selected gate inputs, then our testing procedure is run on the affected netlist and the diagnosis outcome is compared with the expected one. It can be seen that in all cases the coverage for single stuck-at faults closely tracks 100%. The number of test vectors provides the test application time (in clock cycles). A network with a flit width of 32 bits, as assumed so far, would therefore take 1104 clock cycles for testing, regardless of the network size. If we assume 64 bit flits, then LBDR testing occurs in parallel with arbiter Switch sub-block Test patterns Test vectors Coverage Table 1: Coverage for single stuck-at faults. Test Cycle Coverage Our 864 - 1104 99.3% [20] 3.88 x 102 - 2.89 x 103 97.79% [21] 4.05 x 105 95.20% [13] 2.74 x 103 99.89% [14] 9.45 x 103 - 3.33 x 104 98.93% [22] 5 x 104 - 1.24 x 108 N.A. [9] 320 99.33% [10] 200 x 103 full (no exact numbers) Table 2: Test application time and coverage of different testing methods. Table 3: Coverage for multiple random stuck-at faults. testing and total test time reduces to 864 cycles. These numbers compare favorably with previous work, as Tab.2 shows. Only [20] and [9] in some cases do better. However, [20] does not test the control path while [9] reports 320 cycles for a 3x3 mesh (made of a simplified switch architecture) which however grow linearly with network size. Also, this latter approach makes additional use of BIST logic for the control path not accounted for in the statistics. We feel that area overhead is hardly comparable with previous work since whenever numbers are available, features of the testing frameworks are very different (e.g., control path not tested [20], test patterns generated externally [21, 14], diagnosis missing [21, 13, 14, 22], lack of similar test time scalability [5, 9], NoC architecture with overly costly links [13]). Moreover, the impact of synthesis constraints is never discussed.

Fault Coverage. Fig.30 shows the fault coverage of the baseline channel enhanced with pseudo-random patterns as function of the number of clock cycles. As we can see, the number of clock cycles required to achieve a high coverage increases pseudo-logarithmically. The 96.5% of coverage is reached in 4.000 Figure 29: Breakdown of Area Overhead for Pseudo-Random and Deterministic TPGs. Figure 30: Fault coverage of the baseline channel with pseudo-random pattern as a function of the number of cycles. clock cycles while the 98% after 24.500 cycles. The deterministic based solution performs slightly better than the pseudo-random counterpart achieving the 97% of coverage in 3950 cycles.