Real Benchmarks Sample Clauses

Real Benchmarks. In this section we compare the performance of the private and shared I$ architectures by using two real applications, namely a JPEG decoder and a Scale Invariant Feature Transform (SIFT), a widely adopted algorithm in the domain of image recognition. In particular, our aim is to evaluate the behavior of the two target architectures when considering different types of parallelism at the application level. We thus parallelized our benchmarks with OpenMP, and considering three different examples. The first example expresses data-parallelism at the application level. Thus we focused on the two data-independent computational kernels in JPEG: Dequantization (DQTZ) and Inverse Discrete Cosine Transform (IDCT). With this parallelization scheme all processors execute the same instructions, but over different data sets. In the second example we adopt pipeline parallelism in the same JPEG application, where each of the four stages of JPEG – Xxxxxxx DC, Xxxxxxx AC, Dequantization, IDCT – is wrapped in an independent task assigned to a processor. To keep all the processors busy we execute four pipelines in parallel. The third example considers three main kernels from SIFT: up-sampling, Gaussian convolution, and difference of Gaussians, all leveraging data-parallelism. In relation with the JPEG data parallel application, SIFT is composed of more complex computational steps that can stress the cache capacity causing more misses. In what follows we carry out two main experiments. We evaluate the performance by (i) varying the cache size and (ii) the L3 latency. Figure 12 shows the results for the first experiment. Here we consider a fixed latency of 50 cycles for the L3 memory, and we vary the cache size. Focusing on the plots on the top part of the figure, for each of the three benchmarks and for the two architectures we show execution time, normalized to the slowest value (i.e. the longest execution time for that benchmark). Looking at the data parallel variant of JPEG it is possible to see that the shared cache architecture performs worse than the private cache architecture. We would expect the SIMD parallelism exploited by this application to be favoured on the shared cache architecture, so this finding is seemingly counterintuitive. The reason for this loss of performance is to be found in an increased average hit cost, due to the banking conflicts in the instruction cache described in the previous section. So if we mathematically model the overall execution time of ...