Symmetric Multiprocessing (SMP Sample Clauses

Symmetric Multiprocessing (SMP. An SMP processor contains several identical cores. Each core is similar to the processor found in a uniprocessor system. The SMP processor includes additional logic to allow the cores to operate simultaneously. Due to the identical cores, an SMP processor on its own is an example of a homogeneous multiprocessing system implementing the MPMD threading model. An SMP processor can also be combined with other processors or accelerators to form a heterogeneous multiprocessing system. The cores of an SMP system have a single view of memory: changes to memory made on one core are visible to the others. Each architecture supporting SMP defines a memory ordering model – a set of rules defining precisely when changes to memory made by one processor are made visible to the other processors. The memory system of an SMP processor is similar to that found in uniprocessor systems – a hierarchy of one or more levels of cache and main memory. Each level of cache may be duplicated by all processors, shared by all processors, or fall somewhere between these extremes. Where multiple instances of a cache exist at a given level, a cache coherency mechanism is usually used to ensure that the memory ordering model is honoured. This is a tradeoff: the cache coherency system imposes area, power and performance costs to provide a memory ordering model that is easier for the programmer to use. More programmer-friendly memory ordering models typically impose a higher cost in the cache coherency mechanism. An architecture supporting SMP includes facilities to allow synchronization between pro- cessors. These usually take the form of composite atomic instructions (e.g. swap, compare-and- swap, add, subtract, etc.) or atomic primitives (e.g. load-locked, store-conditional) which can be combined with data processing operations to produce the desired effect. Typically, user programs running on an SMP machine have a virtualized view of memory, controlled by OS software and implemented by the memory management unit (MMU) in each processor. If desired, threads running on different processors can use the same MMU configuration, and thus share an identical view of memory. As each core supports a single thread, that thread has performance comparable to a similar uniprocessor. This means that in general performance is relatively high, but memory accesses within a given thread need to demonstrate good temporal and spatial locality to make the most of the cache system and hence maximize performance...