Summary of Research. Fabrication. The fabrication process is similar to [2] except for the PtSe2 synthesis methods. The detailed structure of a single device is shown in Figure 1(a). After the deposition of Al2O3 as the gate dielectric, the chip was cleaned by acetone, isopropyl alcohol, and deionized water, before drying with N2. After it was loaded into a DCA Instruments R450 MBE reactor, it was outgassed for 30 min at 130°C, Growth commenced at 200°C under a Pt flux of 9.2 × 1012/cm2·s and an Se flux of 1.6 × 1014/cm2·s. The Pt and Se fluxes are generated by an electron gun and a Xxxxxxx cell, respectively. After growing for 339 s under both Pt and Se fluxes, the PtSe2 was annealed at 400°C for 30 min under the Se flux alone to enhance its crystal quality. The resulting PtSe2 is approximately three monolayers (2-nm thick) and (001)-oriented with a high degree of in-plane rotational twin formation.
Summary of Research. The Additional Research Program will be undertaken in three phases. All three phases will begin immediately and will be undertaken concurrently, but continuation of the Additional Research Project is dependent upon a positive outcome of Phase 1 and continuation of Phase 3 is dependent upon a positive outcome in Phase 2.
Summary of Research. The Research for the development of the 3/6 gene signatures will be undertaken in three phases. As noted below, commencement of research on certain phases requires a positive outcome in certain prior phases.
Summary of Research. The objective of this analysis is to assess:
Summary of Research. In summary, a fully transparent submicron TFT based on BaSnO3 has been fabricated with a high drain current and on/off current ratio. This breakthrough is made possible by (1) high mobility bare films in combination with (2) the development of a micrometer-scale etching method that preserves the surface roughness, conductivity, and mobility of BaSnO3 films. These results demonstrate the tremendous potential of BaSnO3 for the future of transparent electronics. The channel is 0.3 µm long and 0.93 µm wide. This is the first demonstration of a submicron scale BaSnO3-based field effect transistor with complete depletion at room temperature. This result has been published in APL Materials January 2020. Two patent applications have been filed on the reactive ion etching of BaSnO3. References: [1] J. Park, X. Xxxx, X. Xxxxxx, X. Xxx, X.-X. Xxxx, X. Xxxxxxx, X.-X. Wang, X. Xxxxxxxxxx, X. Xxxxx, X. Xxx, X. Xxxx, H. G. Xxxx, and X. X. Xxxxxx, APL Mater. 8, 011110 (2020) [2] X. X. Xxx, X. Xxx, X. X. Xxx, X. X. Xxx, X. X. Xxx, B.-X. Xxxx, X. X. Xxxx, W.-X. Xxx, X. Xx, X. X. Xxx, and X. Xxxx, Appl. Phys. Exp. 5, 061102 (2012). [3] X. Xxx, X. Xxxx, X. Xx, X. X. Xxx, X. Xxx, X. Xx, X. Xxxx, X. Xxx, X. X. Xxx, and X. Xxxx, APL Mater. 3, 036101 (2015). [4] X. Xxx, X. Xxxxxxx, X. X. Xxxxxxx, X. X. Xxxxxxx, and B. Jalan, ACS Appl. Mater. Interfaces 10, 21061 (2018). [5] X. Xxxx, X. Xxx, and X. Xxxx, Appl. Phys. Lett. 108, 092106 (2016). [6] X. Xxxx, X. X. Xxx, X. Xxx, X. Xxxx, and X. Xxxx, Appl. Phys. Lett. 109, 262102 (2016). [7] X. Xxxx, X. Xxx, X. X. Xx, X. X. Xxxx, X. X. Xxx, and X. Xxxx, Appl. Phys. Lett. 105, 203503 (2014). [8] X. X. Xxx, X. Xxxx, X. Xx, X. Xxx, X. Xxx, X. Xxxx, X. Xxx, X. Xx, X. X. Xxx, and X. Xxxx, APL Mater. 5, 016104 (2017). [9] X. X. Xxx, X. Xxxx, X. Xxx, X. Xx, and X. Xxxx, Appl. Phys. Exp. 9, 011201 (2016). [10] X. Xxxx, U.S. patent application No. 16/706,126, Docket# 1126- 051 (filed, December 6 2019). [11] X. Xxxx, U.S. patent application No. 16/706,126, Docket# 1126- 052 (filed, December 6 2019).
Summary of Research. Beta-phase Ga2O3 has been under intensive research as a promising ultrawide-bandgap semiconductor material. It is expected to have a high breakdown electric field of up to 8 MV/cm due to the sizable bandgap of 4.5-
Summary of Research. With a sizable bandgap higher than that of silicon, two-dimensional (2D) layered materials can be potential candidates for high voltage applications. One of 2D materials, WSe2 is used for enhancement mode p-channel field effect transistors (FETs) for high voltage devices, being patterned by JEOL 6300 in CNF. Ambipolar transport in back-gate WSe2 FETs is often reported in literature, which is a feature of junction-less transistors. However, the breakdown voltage of back-gate WSe2 FETs with overlapping source and drain is found to be limited by the ambipolar transport. In the off-state of WSe2 p-FETs, the voltage across the overlapping drain and gate creates an electron channel
Summary of Research. The proposed micro-coil system is shown in Figure 1. The programmable stimulation sites are implemented by using a programmable switching network to direct the micro-coil current flow. The switching network can be programmed into four states: pass straight through, cross over, short-circuit, or open-circuit. The switches are implemented as pass gates with the NFETs sized at W/L of 1.5 mm/180 nm and PFETs sized at W/L of 2 mm/180 nm. The switches are sized to have a maximum resistance of 2W. With the trace resistance approximately 4W, the maximum coil resistance is 18W, allowing safe operation of the FETs while driving the micro-coil with 100 mA of current. The micro-coil is programmed using a shift register where the programming bits are buffered and routed down the probe to the switching networks. For electrical verification the coil segments are broken out to a multiplexer and brought off-chip to validate the current direction based off the voltage drop throughout the micro-coil. The micro-coils are released and thinned down from the original chip packaging through a series of nanofabrication steps. Aluminum oxide and chrome are deposited (to serve as silicon etching and oxide etching masks respectively) and patterned using conventional photolithography and a combination of wet-etch and plasma etching. The oxide is etched in a CHF3/O2 oxide plasma etch using the Oxford 100 to expose the silicon surface. The exposed topside silicon is etched in the Unaxis 770 using a deep reactive-ion etching (DRIE) process down to the desired thickness of the neural probe (75 µm). The chips are flipped upside-down and the bulk silicon is etched in the same DRIE process until the micro-coils are released from the rest of the chip. The nanofabrication process to release the micro- coils is shown in Figure 3. The released micro-coils are then wire bonded to a carrier PCB, the wire bonds are protected with epoxy, and the entire assembly is coated with around 2 µm of Parylene-C to further encapsulate the micro-coil. The micro-coils were fabricated in a 180 nm 1P6M CMOS process with a probe length and width of 1.9 mm and
Summary of Research. In 3-4 pages, describe the project, methodology and results using the headings below as a guide.
