TABLE LIST. Table 1-1: Control Pins 9 Table 1-2: Hardware Alarm Pins 10 Table 1-3: Management Interface Pins (MDIO) 11 Table 4-1: Voltage Power Supply 16 Table 4-2: Optional Reference Clock Characteristics 19 Table 4-3: Optional Monitor Clock Characteristics 20 Table 4-4: CFP4 Module Clocking Signals 20 Table 5-1: CFP4 Mechanical Characteristics 26 Table 5-2: CFP4 Module Insertion, Extraction Forces 26 Table 5-3: Optical Connectors 28 Table 5-4: CFP4 Host Connector Assembly 29 Table 5-5: CFP4 4x25Gbpt/s Pin Map 31 Table 5-6: CFP4 Bottom Row Piin Description for 4x25 Gbit/s Applications 32 Table 5-7: CFP4 Bail Latch Color Coding 33
TABLE LIST. Table 1-1: Control Pins 9 Table 1-2: Hardware Alarm Pins 10 Table 1-3: Management Interface Pins (MDIO) 11 Table 4-1: Voltage Power Supply 16 Table 4-2: Optional Reference Clock Characteristics 19 Table 4-3: Optional Monitor Clock Characteristics 20 Table 4-4: CFP4 Module Clocking Signals 20 Table 5-1: CFP4 Mechanical Characteristics 26 Table 5-2: CFP4 Module Insertion, Extraction Forces 26 Table 5-3: Optical Connectors 28 Table 5-4: CFP4 Host Connector Assembly 29 Table 5-5: CFP4 4x25Gbpt/s Pin Map 31 Table 5-6: CFP4 Bottom Row Piin Description for 4x25 Gbit/s Applications 32 Table 5-7: CFP4 Bail Latch Color Coding 33 FIGURE LIST Figure 1-1: CFP4 Functional Block Diagram 8 Figure 2-1: Reference +3.3V LVCMOS Output Termination 12 Figure 2-2: Reference 3.3V LVCMOS Input Termination 13 Figure 2-3: Reference MDIO Interface Termination 14 Figure 4-1: High Speed I/O for Data and Clocks 16 Figure 4-2: CFP4 Module Optional Loopback Orientation 17 Figure 4-3: Example of Clocking for 4 x 25 Gbit/s CFP4 Applications 21 Figure 4-4: Example of Clocking for 4 x 10 Gbit/s CFP4 Applications 21 Figure 5-1: CFP4 Module & CFP4 Module Mated in Host Quad Port System 22 Figure 5-2: Host Cage System and Mounting Method Overview 22 Figure 5-3: CFP4 Module Plug Connector Assembly 23 Figure 5-4: CFP4 Quad Port Host Connector Cover Assembly 23 Figure 5-5: CFP4 Host Connector Assembly 24 Figure 5-6: CFP4 Pin Map Connector Engagement 24 Figure 5-7: CFP4 Module Dimension Overview 25 Figure 5-8: Riding Heat Sink 27 Figure 5-9: Host Cage Top Surface Opening 27 Figure 5-10: CFP4 Connector Pin Map Orientation 30 Figure 5-11: CFP4 Module Label Recess 33 REFERENCE DOCUMENTS [1] CFP MSA Hardware Specification, Revision 1.4, June 7, 2010. [2] CFP MSA CFP2 Hardware Specification, Revision 1.0, July 31, 2013. [3] CFP MSA Management Interface Specification, Version 2.4, March, 2015. [4] IEEE P802.3bm, 40Gbit/s and 100Gbit/s Operation Over Fiber Optic Cables Task Force, xxxx://xxx.xxxx000.xxx/3/bm/index.html [5] IEEE Std 802.3TM-2012, Annexes 83A, 83B, and 86A. [6] IEEE Std 802.3TM-2012, Cl. 45, Management Data Input/Output (MDIO) Interface. [7] ITU-T Recommendation G.709 (2012) Interfaces for the Optical Transport Network (OTN). [8] ITU-T Recommendation G.707 (2007) Network node interface for the synchronous digital hierarchy (SDH). [9] OIF-CEI-3.0, xxxx://xxx.xxxxxxx.xxx/public/documents/OIF_CEI_03.0.pdf [10] SFF Committee INF-8077i 10 Gigabit Small Form Factor Pluggable Module [11] SFF Committ...
TABLE LIST. Table 2-1: Control Pins 9 Table 2-2: CFP2 Module Power Classes defined by Hardware Interlock 14 Table 2-3: Hardware Alarm Pins 15 Table 2-4: Management Interface Pins (MDIO) 16 Table 2-5: Timing Parameters for CFP Hardware Signal Pins 16 Table 4-1 Voltage power supply 22 Table 4-2: Optional Reference Clock Characteristics 27 Table 4-3: Optional Transmitter & Receiver Monitor Clock Characteristics 29 Table 4-4: CFP2 Module Clocking Signals 19 Table 5-1: CFP2 Mechanical Characteristics 42 Table 5-2: CFP2 Module Insertion, Extraction Forces 43 Table 5-3: Optical Connectors 28 Table 5-4 CFP2 Host Connector Assembly 29 Table 5-5: CFP2 N x 25 Gbit/s Pin-Map 58 Table 5-6: CFP2 10 x 10 Gbit/s Pin-Map 50 Table 5-7: CFP2 Bottom Row Pin Description for N x 25 Gbit/s applications Error! Bookmark not defined. Table 5-8: CFP2 Bottom Row Pin Description for 10 x 10 Gbit/s applications 58 Table 5-9: CFP2 Bail Latch Color Coding 59
