TABLE LIST. Table 1-1: Control Pins 9 Table 1-2: Hardware Alarm Pins 10 Table 1-3: Management Interface Pins (MDIO) 11 Table 4-1: Voltage Power Supply 16 Table 4-2: Optional Reference Clock Characteristics 19 Table 4-3: Optional Monitor Clock Characteristics 20 Table 4-4: CFP4 Module Clocking Signals 20 Table 5-1: CFP4 Mechanical Characteristics 26 Table 5-2: CFP4 Module Insertion, Extraction Forces 26 Table 5-3: Optical Connectors 28 Table 5-4: CFP4 Host Connector Assembly 29 Table 5-5: CFP4 4x25Gbpt/s Pin Map 31 Table 5-6: CFP4 Bottom Row Piin Description for 4x25 Gbit/s Applications 32 Table 5-7: CFP4 Bail Latch Color Coding 33
TABLE LIST. Table 2-1: Hardware Control Pins 12 Table 2-2: Hardware Alarm Pins 14 Table 2-3: Management Interface Pins (MDIO) 15 Table 2-4: Optional MOD_SELn Timing Parameters 18 Table 4-1: Voltage Power Supply 22 Table 4-2: Optional Reference Clock Characteristics 26 Table 4-3: Optional Monitor Clock Characteristics 27 Table 4-4: CFP8 Module Clocking Signals 28 Table 5-1: CFP8 Mechanical Characteristics 36 Table 5-2: CFP8 Module Insertion, Extraction Forces 37 Table 5-3: Optical Connectors 39 Table 5-4: CFP8 Host Connector Assembly 40 Table 5-5: CFP8 Pin Map 42 Table 5-6: CFP8 Top Row Pin Descriptions 43 Table 5-7: CFP8 Bottom Row Pin Descriptions 45 Table 5-8: CFP8 Bail Latch Color Coding 48 Figure 1-1: CFP8 Functional Block Diagram 11 Figure 2-1: Reference +3.3V LVCMOS Output Termination 16 Figure 2-2: Reference 3.3V LVCMOS Input Termination 17 Figure 2-3: Reference MDIO Interface Termination 17 Figure 2-4: Optional MOD_SELn Timing Diagram 18 Figure 3-1 PHYADR Setup Sequence for Optional Shared MDIO bus 20 Figure 4-1: High Speed I/O for Data and Clocks 23 Figure 4-2: CFP8 Module Optional Loopback Orientation 25 Figure 4-3: Example of Clocking for 16 x 25 Gb/s CFP8 Applications 29 Figure 4-4:Example of Clocking for 8 x 50 Gb/s XXX-4 CFP8 Applications 29 Figure 5-1: CFP8 Module & CFP8 Module Mated in Single and Dual Port Systems 30 Figure 5-2: Host Cage System and Mounting Method Overview 31 Figure 5-3: CFP8 Module Plug Connector Assembly 32 Figure 5-4: CFP8 Single & Double Port Host Connector Cover Assemblies 33 Figure 5-5: CFP8 Host Connector Assembly 33 Figure 5-6: CFP8 Pin Map Connector Engagement 34 Figure 5-7: CFP8 Module Dimension Overview 35 Figure 5-8: Riding Heat Sink 38 Figure 5-9: Host Cage Top Surface Opening 39 Figure 5-10: CFP8 Optical Connector Position 40 Figure 5-11: CFP8 Connector Pin Map Orientation 41 Figure 5-12 CFP8 Pin Map for Multiple Configurations 47 Figure 5-13: CFP8 Module Label Recess 48 [1] CFP MSA Hardware Specification, Revision 1.4, June 7, 2010. xxxx://xxx.xxx- xxx.xxx/Xxxxxxxxx/XXX-XXX-XX-Xxxx-xxx0-00.xxx [2] CFP MSA CFP2 Hardware Specification, Revision 1.0, July 31, 2013. xxxx://xxx.xxx- xxx.xxx/Xxxxxxxxx/XXX0_XX-Xxxx-xxx0.0.xxx [3] CFP MSA CFP4 Hardware Specification, Revision 1.1, March 18, 2015. xxxx://xxx.xxx- xxx.xxx/Xxxxxxxxx/XXX-XXX_XXX0_XX-Xxxx-xxx0.0.xxx [4] CFP MSA Management Interface Specification, Version 2.4, June 8, 2015. xxxx://xxx.xxx- xxx.xxx/Xxxxxxxxx/XXX_XXX_XXX_X0x0x00x.xxx (to be updated) [5] IEEE P802.3bs, ...
TABLE LIST. Table 2-1: Control Pins 9 Table 2-2: CFP2 Module Power Classes defined by Hardware Interlock 14 Table 2-3: Hardware Alarm Pins 15 Table 2-4: Management Interface Pins (MDIO) 16 Table 2-5: Timing Parameters for CFP Hardware Signal Pins 16 Table 4-1 Voltage power supply 22 Table 4-2: Optional Reference Clock Characteristics 27 Table 4-3: Optional Transmitter & Receiver Monitor Clock Characteristics 29 Table 4-4: CFP2 Module Clocking Signals 19 Table 5-1: CFP2 Mechanical Characteristics 42 Table 5-2: CFP2 Module Insertion, Extraction Forces 43 Table 5-3: Optical Connectors 28 Table 5-4 CFP2 Host Connector Assembly 29 Table 5-5: CFP2 N x 25 Gbit/s Pin-Map 58 Table 5-6: CFP2 10 x 10 Gbit/s Pin-Map 50 Table 5-7: CFP2 Bottom Row Pin Description for N x 25 Gbit/s applications Error! Bookmark not Table 5-8: CFP2 Bottom Row Pin Description for 10 x 10 Gbit/s applications 58 Table 5-9: CFP2 Bail Latch Color Coding 59
