Software Architecture. The hosted online vending system software must be hosted in at least a Tier 3 data centre.
Software Architecture. 21 4.6.1 Containers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.6.2 Components - micro-ROS Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.6.3 Components - micro-ROS Agent 30 4.7.1 Node interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.7.2 Publisher and subscribers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.7.3 Service, server and client . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.7.4 Parameters manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.7.5 Graph manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.7.6 Timers and Clocks interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.7.7 Executor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.7.8 Lifecycle and system modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.7.9 Logging utilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.7.10 Agent core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.7.11 Parameter server . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.7.12 Graph server . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.8.1 micro-ROS Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.8.2 micro-ROS Agent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.7 External Interfaces 31 4.8 4.9 Infrastructure Architecture 38 4.9.1 infrastructure 38 4.10 Deployment 38 4.10.1 Deployment 38 4.10.2 Build system 40 4.10.3 Profiles 40 4.10.4 Test system 41 5 Appendix 41 5.1 A1 Related documents 41 References 42 1 Acronyms Acronym Explanation CDR Common Data Representation DDS Data Distribution Service FSM Finite-State Machine HW Hardware IDL Interface Definition Language IRQ Interrupt Request MCU Microcontroller Unit MPU Microprocessor Unit MTU Maximum Transmission Unit NTP Network Time Protocol OMG Object Management Group OS Operating System OSS Open Source Software QoS Quality of Service PTP Precision Time Protocol ROS Robot Operating System RPC Remote Procedure Call RTOS Real Time Operating System RTPS Real-Time Publish-Subscribe XRCE Extremely R...
Software Architecture. Overview
Software Architecture. The software consists of a number of threads which are running on the 2 processors, each managing processes with a number of specific performance requirements. Not all the software threads have been implemented inside this project. On the LINK processor [2 in figure 12] a scheduler is managing the processor item allocation and the priorities of each of these processes. This scheduler is interfacing to a K-API [Kernel API]. On the APP processor [1 in figure 12] an OS will be implemented. This OS remains to be selected. An appropriate wireless sensor operating system. Operating system alternatives are RIOT, Contiki, TinyOS, Linux… The RIOT operating system is a promising recent open source European initiative focused on embedded nodes networks that requires low power and computational resources. Short description of the software components: at networking layer: BTLE Link layer interfacing to an HCI –API. HCI is also accessible as HCI commands on the SPI interface. The BTLE link layer is Bluetooth specification V4.0, V4.1 and V4.2 compliant. 802.15.4 MAC layer interfacing to a proprietary 802.15.4-API. Also accessible on the platform SPI interface. The MAC layer is compliant with the 802.15.4 standard. The ZIGBEE and BTLE thread are based on external solutions. SPI external interface. SPI-based debugger that can survive the deep sleep mode. Problem with JTAG debugger is that they require the JTAG interface to be powered in order to be able to run the debugger. This is an issue in this device, as the goal is to put the device in a sleep state most of the time where the JTAG is not powered. The issue can be resolved by doing a SPI debugger. Application layer on the application processor. Communicates with the LINK processor over a COMs API. Following table summarizes the software memory [program and data] sizes. Link Layer Developed 16 KBYTE 802.15.4 MAC 50% developed 16KBYTE SCHEDULER Developed 15 KBYTE BTLE HOST External 38KBYTE BTLE Profiles External Partner ZIGBEE External 55KBYTE
Software Architecture. This must be prepared and submitted according to the standards defined in the Construction and Implementation Deliverables section.
Software Architecture. The Figure 2 gives an overview of the use case architecture and the interfaces between the different modules.
Software Architecture. All DSP software conforms to the VP Open software architecture. All DSP modules work on 64 sample blocks of data (8 ms). in each 8 ms interval, the DSP performs the following functions:
1. Reads data from the buffered serial ports. This includes timeslot data as well as commands from the Core Processor.
2. Interprets the Core Processor commands into calls to selected DSP functions.
3. Sends data to the buffered serial ports. This includes voice data as well as status to the Core Processor. The scheduling of these functions is handled by the Command and Status Module (CSM) according to the VP Open specification. Detailed description of the code is presented in the following sections, in addition to [3].
Software Architecture. The content delivery software consists of following main components: FIBRE control framework to provide the slice of OpenFlow enabled devices (packet, optical), media server and virtual machines to host software’s. Media Solution: FOGO 4k Player and Streamer. The FOGO is a proprietary solution and will be available till the end of the FIBRE project. POX controller: this is the SDN controller which runs on top of the experimenter slice. It utilizes the OF Interface to control the slice resources. The controller application is hosted over python DJANGO framework. The DJANGO framework consists of application called POX_CW which houses the content delivery software and interfaces. The main modules of the controller are as follows.
Software Architecture. The System Architecture Deliverable contains information of how the software System is designed and constructed. It explains how the code is structured using objects, models and services and the core technology used. The document content contains illustrations, diagrams and narrative text. • Infrastructure Specifications. The Infrastructure Specifications Deliverable contains information regarding the physical or virtual server hardware environment and includes basic server specification information like the operating System version. • Analysis and Design Summary. The analysis and design summary Deliverable must contain the following information: o Description of issue or enhancement; o Summary of analysis conducted to determine the root cause of the bug and proposed changes to software code or configuration; o If a bug, description of the steps to reproduce the issue; and o Recommended changes to be made to software code, architecture, configuration.
Software Architecture. Following the comments from the first year technical review, this appendix has been added to describe the software modules that will be developed in the prototype of the COSIGN control layer. The objective is to highlight the components that will be implemented in the OpenDaylight framework as new OpenDaylight plugins developed from scratch or as extended versions of already existing OpenDaylight plugins. In this latest case, this section will provide details about the modifications and enhancements that will be needed to meet COSIGN requirements. Moreover, some components related to the composition and delivery of virtual optical slices will be implemented as OpenVirteX plugins and will require the extension of the OpenVirteX platform in support of optical resources, as documented in the next tables. The outcomes documented in this section are the result of the software design activities carried out in T3.1, T3.2 and T3.3 from M13 to M15. These activities have taken as input the functional architecture documented in the previous sections of this document and, for each functional component defined in Section 4.1, have defined a set of software modules which will implement the associated control plane functions (functions derived from the requirements, as detailed in Table 2). The list of the resulting software modules is summarized in Table 5, which also specifies the prototype release(s) where each module will be included (i.e., preliminary release in D3.3 “SDN controller for DC optical network virtualization and provisioning software prototypes: Preliminary release” at M24 and/or final release in D3.4 “SDN controller for DC optical network virtualization and provisioning software prototypes: Final release” at M30). The following tables describe in details each software module, defining the software architecture which marks the milestone MS14 (Intra-DC control plane high-level architecture), planned at M15.
