Production Testing. Operations for the controlled flow of Hydrocarbons to the surface for the purpose of measuring flow rates or flowing pressures, or gaining other subsurface data.
Production Testing full rollout;
Production Testing. The Engineer will test at the frequency listed in the Department’s Guide Schedule of Sampling and Testing and this specification. The Engineer may suspend production if production tests do not meet specifications or are not within operational tolerances listed in Table 11. Take immediate corrective action if the Engineer’s laboratory-molded density on any sample is less than 95.0% or greater than 98.0%, to bring the mixture within these tolerances. The Engineer may suspend operations if the Contractor’s corrective actions do not produce acceptable results. The Engineer will allow production to resume when the proposed corrective action is likely to yield acceptable results. The Engineer may use alternate methods for determining the asphalt binder content and aggregate gradation if the aggregate mineralogy is such that Tex-236-F does not yield reliable results. Use the applicable test procedure if an alternate test method is selected. Individual % retained for #8 sieve and larger Tex-200-F or Tex-236-F Individual % retained for sieves smaller than #8 and larger than #200 % passing the #200 sieve Laboratory-molded density Tex-207-F Laboratory-molded bulk specific gravity In-Place air voids VMA Tex-204-F Moisture content Tex-212-F, Part II Theoretical maximum specific (Rice) gravity Tex-227-F Asphalt binder content Tex-236-F Hamburg Wheel test Tex-242-F Recycled Asphalt Shingles (RAS)1 Tex-217-F, Part III Asphalt binder sampling and testing Tex-500-C Tack coat sampling and testing Tex-500-C, Part III Boil test Tex-530-C 1. Testing performed by the Construction Division or designated laboratory.
Production Testing. Once the SOC accelerator has been manufactured, these prototypes must then undergo testing to ensure the IP developed on the Altera development platform is successfully ported to the new hardware. The different hardware features of this board must be tested to ensure no unforeseen problems have arisen during the manufacturing process.
Production Testing. The hardware was first tested in a static condition, i.e. all power supplies are tested to fall within design tolerances at no-load and full-load. The Built-in-self-test is run selecting high dynamic load conditions for dynamic testing. Typically, this is a combination of memories tested using F-0-F patterns and high frequency processor switching with the FPGA. The FPGA design has variable current load modules (known as burners) that can be enabled and disabled to alter the dynamic load in the FPGA. This simulates different levels of customer usage. During such testing, all power supplies are monitored using an Oscilloscope with low frequency filtering enabled to ensure no noise or voltage excursions beyond nominal limits are observed. Also, all power supplies are observed using AC coupling to check high frequency stability. During BIST, power supplies are monitored to ensure they are within specification at all times during testing. Additionally, power supplies are margined up and down to ensure they are correctly monitored by the on-board UCD9090 device. This is done repeatedly during testing to ensure stability. The following tests are repeated throughout the production test period (typically 3½ hours). Onboard Power Load Margin Low Step through variable current loads (8 steps minimum current to maximum) Nominal Nominal Margin High Margin High Margin Low Minimum Step through variable current loads (8 steps minimum current to maximum) Minimum Step through variable current loads (8 steps minimum current to maximum) Minimum Table 1: list of repetitive tests These measurements are recorded as part of normal BIST testing.
Production Testing. During design the Flash interface was extensively tested through a combination of software and firmware, verifying programming, erasure and verification functionality. After manufacture, the Flash memory is programmed with a default program and used within the production environment to program the FPGA, thus proving it is functional and connected.
Production Testing. Memories were tested using a variety of access patterns and data patterns to fully characterize the interfaces. In all cases, the tests were run at nominal frequency (2133 MTPS/1066MHz) and at a higher frequency (2400 MTPS/1200MHz). Memory tests were run with power supplies margined high, nominal and low. The patterns used for testing are shown below. Pattern Description Typical Use Sequence A monotonically rising sequence of numbers e.g. 0 1 2 3 Pseudo-Random sequence of 32 Used for basic debug. Allows easy identification of repeated numbers, address bit errors etc. Tests all possible sequences of 1s and 0s on all Rolling 1 Rolling 0 bit numbers. Sequence of values with a single set bit which moves from bit 0 to bit 31 before starting again at bit 0. Sequence of values with a single unset bit which moves from bit 0 to bit 31 before starting again at bit 0. Sequence of 0xffffffff followed by 0x00000000 repeated. Sequence of 0x55555555 followed by 0xaaaaaaaa repeated. lines in the minimum time. Useful for showing signal integrity and reflection issues. Finds interconnected data bits and can show crosstalk between bits more clearly than PRBS. Can also clearly show stuck low bits. Finds interconnected data bits and can show crosstalk between bits more clearly than PRBS. Can also clearly show stuck high bits. Very high switching currents and simultaneous switching. Maximal test for I/O power supplies. Like F-0-F but adjacent bits are always inverses thus dynamic power is lower. Can show weak crosstalk between lines, or some specific driver issues. Table 3: patterns used for testing
Production Testing. The production BIST runs using communications across the PCIe interface, and also checks that this interface has successfully trained to Gen 3, x8. The appropriate section of the BIST report is copied below. Table 5: production testing result
Production Testing. During production, the QSFP28 cages are populated with QSFP-SR4-40G transceivers connected together using GMP-B-1-12-F-MM4-LS-MTP/PC-MTP/PC-1M fibre optic patch cord. This allows for full transmit and receive testing of the eight QSFP transceivers. The BIST sets up the FPGA transceivers and enables the channels. It then locks the receivers using test patterns. A single error is injected on each transmitter to ensure the loopback is complete and that errors can be detected. During the full BIST, the error status of all receivers is monitored. Any failure results in reject of the card. The lines related to QSFP testing are reproduced below. Table 6: QSFP testing report The BIST developed for the SOC accelerator does not include QSFP28 testing by default as it is not possible to assume that a loopback cables are inserted. In fact, it may be that the board is connected to other equipment and so any BIST could cause problems. Therefore, testing of the serial links was done for a single card in isolation and will not be performed on the full OPERA heterogeneous system.
Production Testing. The production BIST is designed to maximally stress the product (within normal operating limits) and so ensures that all features of the product (memory, PCIe, processing power and QSFP28) are operating at full rate, continuously and simultaneously without failure. It further stresses these features by margining the power supply to simulate a higher stress situation.
